This application claims the benefit of German application number 101 24 176.3, filed May 17, 2001, currently pending, the disclosure of which is hereby incorporated by reference in its entirety.
The present invention relates to an apparatus and a method for reducing reflexions in a memory bus system in which data are sent and received.
In conventional buses, such as memory subsystem buses in computer systems, reflexions or multiple reflexions typically occur in the bus during the sending and receiving of data at the connecting points of components such as, for example, memory components. Further causes for reflexions are, in general, branches of the bus with a different load, changes in impedance inside the bus and, in general, the topology of the bus.
In the prior art, such reflexions are usually reduced with the aid of passive or active terminations, the active terminations being optimized only for a specific operating point in the working range of the bus, and reducing the reflexions optimally only there.
A problem in the prior art therefore consists in that the measures for reducing reflexions in buses do not reduce reflexions for a wide working range of the bus. Such a working range is determined, for example, by the distinguishability of the sent and received data, that is to say, for example, the bit pattern, the temporal changes in the bus characteristics and the connecting characteristics of components on the bus, and the frequency of the sent and received data signals. If the reflexions are not adequately reduced, this can lead, inter alia, to a loss in the temporal alignment of the data in the bus and, for example, in the case of high frequencies to smearing or rounding of binary signal edges.
The object of the present invention therefore consists in creating an apparatus and a method for reducing reflexions in a bus for transmitting data, which permit a reduction in reflexions over the entire working range of the bus.
This object is achieved by means of an apparatus for reducing reflexions in a bus for transmitting data in accordance with claim 1, a controller for a bus in accordance with claim 16, a memory component in accordance with claim 17, and a method for reducing reflexions in a bus for transmitting data in accordance with claim 18.
One advantage of the apparatus and the method of the present invention consists in that the same permit a reduction in reflexions in a bus over a wide working range of the bus in conjunction with variations in the frequency of the data signal and the characteristics of the bus etc.
A further advantage of the apparatus and the method of the present invention consists in that in the case of high frequencies, in particular, reflexions are reduced which can effect strong smearing or rounding of signal edges.
Advantageous developments and improvements of the apparatus specified in claim 1 and of the method specified in claim 17 are to be found in the subclaims.
In accordance with a preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged in order to control the impedance as a function of the evaluation result in such a way that the latter is constant over the frequency.
An advantage of this preferred development consists in that, particularly in the case of high frequencies, smearing or rounding of signal edges is avoided by keeping the impedance constant over the entire frequency range.
In accordance with a further preferred development of the apparatus of the present invention, the device for receiving is a detecting amplifier which detects the settling time and the hold time of data, which are represented by the test signal, at the device for receiving.
In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is, furthermore, arranged in order to set the impedance in such a way that the settling time and the hold time are optimized.
In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged, furthermore, in order to set the impedance in such a way that overshooting and undershooting in the bus are reduced.
In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting is arranged, furthermore, in order to set the transmission strength and the time profile of the transmission strength of the device for sending in such a way that the data alignment in the bus is maintained.
In accordance with a further preferred development of the apparatus of the present invention, the device for evaluating and setting has a memory in which setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals are stored.
In accordance with a further preferred development of the apparatus of the present invention, the test signal is a digital signal which has a predefined bit pattern.
In accordance with a further preferred development of the present invention [sic], the impedance is a series impedance which has a first input, a second input and an output which is connected to the output, there being connected between the first input and the output a first impedance whose impedance value can be controlled, and between the output and the second input a second impedance whose impedance value can be controlled.
In accordance with a further preferred development of the present invention [sic], the first impedance has a first transistor whose impedance value can be controlled, and the second impedance has a second transistor whose impedance value can be controlled.
In accordance with a further preferred development of the apparatus of the present invention, the first transistor is connected to a first power supply in a controllable fashion via a third transistor, which is controlled by the device for evaluating and setting, and the second transistor is connected to a second power supply in a controllable fashion via a fourth transistor, which is controlled by the device for evaluating and setting.
In accordance with a further preferred development of the apparatus of the present invention, the first, second, third and fourth transistors in each case have a control input which is connected to the device for evaluating and setting.
In accordance with a further preferred development of the apparatus of the present invention, the first and the second transistor in each case have a JFET transistor, and the third and the fourth transistor in each case have a MOSFET transistor.
In accordance with a further preferred development of the apparatus of the present invention, the bus has a memory subsystem bus to which memory components can be connected.
In accordance with a further preferred development of the present invention [sic], the memory components have dynamic random access memory (DRAM) memory components.
In accordance with a preferred development of the method of the present invention, the steps of evaluating and setting have the step of controlling the impedance as a function of the evaluation result in such a way that the impedance is constant over the frequency.
In accordance with a further preferred development of the method of the present invention, the step of receiving further has [lacuna] the detection of the settling time and the hold time of data which are represented by the test signal.
In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the impedance in such a way that the settling time and the holding time are optimized.
In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the impedance in such a way that overshooting and undershooting in the bus are reduced.
In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of setting the transmission strength and the time profile of the transmission strength during the step of sending in such a way that the data alignment in the bus is maintained.
In accordance with a further preferred development of the method of the present invention, the steps of evaluating and setting further have the step of storing the setting values for the impedance, the transmission strength and the time profile of the transmission strength for assigned test signals.